This invention relates to manufacturing semiconductor integrated circuits and more particularly to integrated circuit layout efficiency.
Integrated Circuits (IC) are manufactured on semiconductor material such as either Silicon or Germanium. Silicon being the major material because of its unique property of providing the dielectric material Silicon Dioxide (Si02) derived by exposing it in Oxygen environment. Integrated Circuits will be designed with the aid of simulators. Later the design will be transferred to the Silicon in the form of Layout. Layout is the physical representation of an IC and consists of polygons in different masks. Each mask defines different electrical property. Stacking different mask information on Silicon, results in an interconnection of devices such as MOS transistor, diode, bipolar, resistor and capacitor. To manufacture a good quality device on Silicon with a reasonable yield, few constraints are imposed both from manufacturing and yield point of view. These constraints are termed as Design rules. Design rules are guidelines that specify the minimum dimensions and spacing for the different layers for a reliable device. They are fundamentally derived from constraints in device fabrication process and other physical layout considerations. Violating a design rule may result in a non-functional circuit else will reduce the lifetime of the circuit. Hence a designer needs to adhere to these design rules at any cost. Verifying the layout geometry for compliance of the design rules is called Design Rule Check (DRC). Extracting the device information and interconnect information from the layout geometry is called Schematic Verification (SV). Layout Verification (IV) Software is used to perform DRC and SV on the layout geometry. The extracted devices from SV are stored and will be compared against the design electrical netlist for conformance. Later layout geometry will be converted to the mask and will be shipped to the fabrication center for manufacturing.
Masks will be printed on glass plate with a chromium coating on it called as a reticle. Each reticle may contain more number of device images depending on the size of the device. Each mask defines a unique reticle. Hence different reticles for respective layers will be used for fabrication.
Transferring reticle information to Silicon is called a xe2x80x9cshot.xe2x80x9d The complete silicon wafer is exposed with certain number of shots. If the number of shots on a wafer is reduced we will be saving lot of time and money.
Another factor in determining the cost of the IC is the Silicon wafer area used by a device. Effectively using the available area of the complete Silicon wafer means no room for wastage. The best technique of packing a layout will result in an efficient layout, which is extremely helpful in reducing the overall cost of that chip.
At present there is no mechanism available that can really measure and provide a meaningful report of the layout compactness and packing density considering the process constraints.
In the prior art are the following methods.
1. Gate count method is used by the place and route tool in estimating the area required for construction of a circuit. An additional 10 to 20% area is sacrificed for routability during the estimation phase for the design to be completed, causing a non-engineering approach. This method measures the whole IC layout area in terms of a standard NAND gate layout area.
a. The above method cannot work for analog layout such as amplifier or comparator where different factors such as matching, shielding, isolation from noise are involved.
b. If the NAND gate itself is not optimum the placement efficiency report generated will be inaccurate.
Using above techniques the estimate of a device can be pessimistic.
2. An analog layout designer uses the standard best practice methodology where they approximately allot the area depending on the complexity of the design. This approximation solely depends on the layout designer""s experience.
3. Some people use visual techniques to determine the underutilized Silicon area. This method does not give a close approximation because of manual intervention.
One of the above methods is determining the benchmark in estimating area for the IC layout. These methods fail to give accurate results of an efficiency report and to set the measurable benchmarks. Because of the under utilization of Silicon area the cost of the IC is also high.
In accordance with one embodiment of the present invention to overcome the above problem an innovative way of measuring and improving the Silicon area efficiency of Integrated Circuit Layout has been developed. In accordance with one embodiment of the present invention the method identifies the seed devices or layers and thereby grows/shrinks it in accordance with the design/process rules. This is the minimum area required for that design. This will be compared against the total available area. The algorithm uses layout verification software to do the layer processing.
The proposed method has the following advantages.
1. The measurement technique is independent of the design rules and Process. This makes the methodology robust.
2. No need to rely on best practices.
3. Due to software intervention; a) No visual check; b) Very accurate; c) Extremely fast; d) Data can be logged for report generation, and e) A benchmark can be set for future devices.
4. Identifies the inefficient area in the layout and provides feedback.